The present invention relates to pipelined hardware for sequentially handling instructions that govern data operations in digital processors, and more particularly to a means for selectively and individually routing instructions through the pipelined hardware.
One known manner of improving data processing speeds in devices for processing digital data, is to configure each computer program instruction as a series of microinstructions presented to a pipeline, and then to perform operations on the microinstructions (or on other data according to the microinstructions) as they progress sequentially through a sequence of pipeline stages in the pipeline. This facilitates concurrent execution of different instructions, one instruction residing in each pipeline stage. An example of a pipelined processor is disclosed in U.S. Pat. No. 4,450,525 (Demuth et al).
While the configuration of microinstructions can vary from one system to another, each microinstruction typically includes a set of multiple bit fields containing control information used by system hardware, including pipelined hardware. Each of the control fields is specifically related to one of the pipeline stages, in that the control field is valid only when the microinstruction resides in the related stage. Particular microinstructions can include one or more control fields relating to one, or all, of the pipeline stages.
The pipeline stages are connected in sequence between a pipeline entry and a pipeline exit. Accordingly, each of the microinstructions progresses sequentially through every pipeline stage, regardless of the number of pipeline stages to which it relates. Consequently, a substantial number of machine cycles are consumed in which microinstructions reside in unrelated pipeline stages, with no operations performed, either on the microinstructions themselves or other data within the processing device.
Therefore, it is an object of the present invention to provide a multiple stage instruction pipeline configured for more effective use of available machine cycles, reducing the number of cycles in which microinstructions reside in unrelated pipeline stages.
Another object is to provide a process for selectively routing microinstructions or control words through a multiple stage instruction pipeline, whereby each microinstruction or control word temporarily resides only in selected stages of the pipeline.
A further object is to provide each of a plurality of microinstructions with a mapping field that identifies the data operations, and therefore the stages, to which the microinstruction relates.
Yet another object of the invention is to provide a means for arbitration among control words or microinstructions competing for access to a particular pipeline stage as they progress through an instruction pipeline.